当前位置：
首页 资源下载
搜索资源 - floating point vhdl
搜索资源列表
-
0下载：
TI6713浮点DSP的DSK的VHDL。比较全面。可以编译运行。-TI6713 floating-point DSP DSK VHDL. More comprehensive. Compiler can run.
-
-
1下载：
浮点加法器的VHDL算法设计 浮点加法器的VHDL算法设计-floating point adder VHDL algorithm design of the floating point adder VHDL Design Algorithm
-
-
0下载：
CAN总线的FPGA实现，用Verilog编写，代码完整，而且有很完善的测试代码，用ISE直接打开，学习FPGA进阶的好项目-CAN Bus FPGA, written with Verilog, code integrity, but also very good test code, using ISE directly open, a good project to learn advanced FPGA
-
-
0下载：
FPGA上浮点算法的实现，用VHDL语言编程-FPGA on the realization of floating-point arithmetic, using VHDL language programming
-
-
0下载：
超前进位加法器是通常数字设计所必备的，本程序为32位超前进位加法器-CLA is usually necessary for digital design, the procedure for 32-bit CLA
-
-
1下载：
一种用VHDL语言描述的浮点前规格化的源代码编程-VHDL language used to describe a floating-point before the standardized programming source code
-
-
0下载：
一种用VHDL语言描述的浮点乘前规格化的源代码编程-VHDL language used to describe a floating-point by the source code before the standardized programming
-
-
0下载：
浮点FFI，的VHDL实现及HDL功能测试方法的研究
附录B加法处理器测试平台代码
附录CFFT处理器的测试平台代码-The floating-point FFI company encourages, implement and function testing HDL VHDL method
The appendix B addition processor test platform code
Appendix CFFT processor test platform co
-
-
0下载：
32位元浮点数加法器,用于以VHDL编写的32位元CPU-32 bits floating-point Add
-
-
0下载：
32位元浮点CPU,用VHDL语言以类似组合语言的方式写成-32 floating-point CPU(VHDL)
-
-
0下载：
16位元浮点数CPU,可作运算,以VHDL编写-16-bit floating point CPU, can be used for computing in order to prepare VHDL
-
-
0下载：
This file is floating point exceptions vhdl program
-
-
0下载：
TIC6000系列 C67浮点DSP处理器 派发站源代码-TIC6000 floating-point DSP processor series C67 station source code distributed
-
-
0下载：
将15位（1，5，9）格式的浮点数转换成18位的定点数-To 15 (1,5,9) floating-point format into 18 fixed points
-
-
0下载：
This a 32-bit floating point unit (FPU), which I developed in a project within the Vienna University of Technology. It can do arithmetic operations on floating point numbers. The FPU complies fully with the IEEE 754 Standard-This is a 32-bit floating
-
-
1下载：
2008-2009年优秀硕士论文之：基于FPGA的高性能32位浮点FFT IP核的开发-Outstanding Master' s thesis 2008-2009: FPGA-based high-performance 32-bit floating-point FFT IP core development
-
-
1下载：
Verilog HDL code for implementation of double floating point architecture. Program takes care of diffent exceptions like overflow, underflow, NaN etc
-
-
0下载：
基于FPGA的单精度浮点除法器vhdl设计程序,分模块程序。-FPGA-based single-precision floating point divider vhdl design program, sub module program.
-
-
0下载：
Floating point vhdl coding
-
-
0下载：
使用vhdl写的32位 64位浮点数加法模块、浮点数乘法模块、浮点数除法模块(Use vhdl write 32-bit 64bit floating-point addition module, floating-point multiplication module, floating-point division module)
-
